Core Concepts¶
Monata is a lightweight EDA framework for circuit design. Its main job is to organize designs, generate reusable views, run simulations through selected backends, and turn results into measurements, specs, sweeps, and optimization loops.
The Monata Mental Model¶
Monata uses a Library/Cell/View hierarchy:
LibraryRegistry
Library
Cell
schematic view
testbench view
netlist view
symbol view
This hierarchy is the center of the user guide. External tools such as ngspice, Native ngspice execution is the first supported backend path. Other tools may be part of the broader circuit toolchain, but the Monata user flow starts from designs and views.
Framework Responsibilities¶
Area |
Monata responsibility |
|---|---|
Design organization |
Register libraries, discover cells, load views |
Circuit authoring |
Use native Python |
Generation |
Generate symbols and netlists from schematic metadata |
Models |
Resolve technology model paths and compiled model artifacts |
Simulation |
Build |
Measurement |
Extract metrics from |
Exploration |
Run sweeps, corners, Monte Carlo, and optimization |
Data Flow¶
A typical design moves through these stages:
Create or register a library.
Create a cell.
Add a schematic view and optional testbench view.
Generate symbol and netlist views.
Attach models and choose a simulator backend.
Create an analysis spec and simulation task.
Execute the task and inspect the result.
Evaluate measurements and specs.
Run sweeps, corners, Monte Carlo, or optimization.
What Belongs Outside the User Guide¶
Backend manuals, compiler details, and device-model history live outside the main user guide:
ngspice backend details: ngspice
Verilog-A compilation: OpenVAF and OSDI, ADMS
model background and compatibility: Device Models