# BSIM Models

## I. What is BSIM

**BSIM** (Berkeley Short-channel IGFET Model) is a series of MOS transistor compact models developed by Professor Chenming Hu's team at the **University of California, Berkeley**. It is the de facto standard SPICE model in the global semiconductor industry today, adopted by all mainstream EDA tools (HSPICE, Spectre, Xyce, NGSpice) and Process Design Kits (PDKs).

> **Compact Model** meaning: Simplifies device physics into a set of analytical equations that can run efficiently in circuit simulators (a single transient simulation may call the model millions of times) while maintaining sufficient accuracy.

---

## II. Evolution Timeline

```
1987        1990        1996           2000          2012         Present
 |           |           |              |             |            |
BSIM1 ──► BSIM2 ──► BSIM3v3 ────► BSIM4 ────► BSIM-CMG ──► GAA Extensions
                    First CMC std     Planar CMOS    FinFET std
                                      workhorse
```

| Model | Year | CMC Standardized | Core Method | Target Device | Applicable Nodes |
|------|------|-----------|---------|---------|------------|
| BSIM1 | ~1987 | — | Vth-based (engineering fit) | Planar MOSFET | >1μm |
| BSIM2 | ~1990 | — | Vth-based (improved) | Planar MOSFET | 0.8–0.5μm |
| **BSIM3v3** | 1996 | First CMC standard | Vth-based + smoothing functions | Planar MOSFET | 0.5μm–0.18μm |
| **BSIM4** | 2000 | CMC standard | Vth-based (greatly extended) | Planar MOSFET | 0.13μm–20nm |
| BSIM-SOI | 2002 | CMC standard | Vth-based | SOI MOSFET | All SOI nodes |
| **BSIM6 / BSIM-BULK** | ~2013 | CMC standard | Charge-based | Bulk planar MOSFET | 28nm and below |
| **BSIM-CMG** | ~2012 | CMC standard (first FinFET) | Surface-potential | FinFET, Nanosheet, GAA | 20nm–3nm |
| BSIM-IMG | ~2012 | — | Surface-potential | Independent multi-gate devices | SOI FinFET |

---

## III. Model Generations Detailed

### 3.1 BSIM1 (~1987)

**Background**: Early SPICE MOSFET models (Level 1/2/3) based on long-channel approximations, unable to accurately describe short-channel effects in sub-micron devices.

**Features**:
- First to systematically incorporate short-channel effects and narrow-channel effects into compact models
- Uses numerous empirical fitting parameters, an "engineering model" rather than "pure physical model"
- Non-smooth transitions between operating regions, poor numerical convergence

**Core Contribution**: Established the "physical formulas + engineering fitting" compact model methodology, laying the foundation for subsequent BSIM series.

---

### 3.2 BSIM2 (~1990)

Improved version of BSIM1, with enhanced mobility degradation and velocity saturation models, more mature parameter extraction procedures. However, still essentially a transitional version, not widely adopted by industry.

---

### 3.3 BSIM3v3 (1996) — First Industry Standard

**Historical Significance**: Selected by **SEMATECH / Compact Model Council (CMC)** in 1996 as the first MOSFET compact model industry standard, ending the chaotic era of vendors maintaining proprietary models.

**Core Technology**:
- Single unified equation based on **threshold voltage (Vth)**
- Introduces **smoothing functions** to unify all operating regions (subthreshold → linear → saturation) into a single continuous equation
- Approximately 60–70 model parameters

**Key Equation Approach**:
```
Vth = Vth0 + γ(√(2φF + VSB) - √(2φF)) - η·Vds    (body effect + DIBL)
Ids = f(Vgs, Vds, Vth, W, L)                      Single equation covers all regions
```

**Limitations**:
- Does not include gate tunneling current (cannot handle <2nm oxide)
- Does not include quantum mechanical effects (polysilicon depletion, inversion layer quantization)
- Imperfect Gummel symmetry test (insufficient for analog/RF design)

---

### 3.4 BSIM4 (2000) — Planar CMOS Workhorse

**Historical Significance**: Selected by CMC in 2000 as industry standard, is the **most widely used and mature MOSFET model**. Almost all 0.13μm–28nm bulk silicon process PDKs provide BSIM4 model cards.

**Relationship with BSIM3v3**: BSIM4 maintains backward compatibility with BSIM3v3, with core I-V still using Vth-based method, but adds numerous deep submicron physical effects.

**BSIM4 Version Evolution and New Physical Effects**:

| Version | Year | New Effects | Corresponding Nodes |
|------|------|---------|---------|
| BSIM4.0 | 2000 | Quantum mechanical effects (QME), polysilicon depletion, gate tunneling current (3 paths), bulk thermal noise | 0.13μm |
| BSIM4.3 | 2003 | Improved gate tunneling model | 90nm |
| BSIM4.4 | 2004 | STI stress effects, trap-assisted diode leakage | 65nm |
| BSIM4.5 | 2005 | Well proximity effect (WPE) | 65nm |
| BSIM4.6+ | 2008+ | Layout-dependent effects (LDE) handled via subcircuit macromodels | 45nm–28nm |

**BSIM4 Parameter Scale**: Approximately **200+** parameters (including all optional effect switches).

**Core Limitations**:
- Vth-based method has derivative discontinuity at Vds=0 (Gummel symmetry failure)
- Insufficient precision for harmonic balance and distortion analysis in analog/RF design
- Cannot describe non-planar devices like FinFETs

---

### 3.5 BSIM-CMG (~2012) — FinFET Era

**Full Name**: Common Multi-Gate

**Historical Significance**: First CMC-standardized **FinFET compact model**, marking the semiconductor industry's transition from planar CMOS to 3D FinFET. Intel 22nm (2011), TSMC 16nm (2014), Samsung 14nm (2015) and other FinFET processes all use BSIM-CMG.

**Core Technology Revolution**: From Vth-based → **Surface-Potential-based**

```
Vth-based (BSIM3/4):
  Ids = f(Vgs, Vth, ...)              ← Calculate Vth first, then substitute into current equation

Surface-potential-based (BSIM-CMG):
  Solve 1D Poisson equation → ψs (surface potential)
  Ids = f(ψs_source, ψs_drain)          ← ψs directly solved from physical equations
```

**Key Physical Effects in BSIM-CMG**:

| Physical Effect | Modeling Method |
|---------|---------|
| Quantum Confinement | Self-consistent Schrödinger-Poisson solution; effective width correction |
| Short-Channel Effect (SCE) | Vth roll-off, subthreshold slope degradation |
| DIBL | DITS (Drain-Induced Threshold Shift) parameter |
| Bulk Conduction | BULKMOD switch, supports Bulk FinFET |
| Mobility Degradation | Vertical field + lateral field mobility model |
| Velocity Saturation | Carrier velocity saturation model |
| Channel Length Modulation (CLM) | Output resistance model |
| GIDL/GISL | Gate-induced drain leakage / gate-induced source leakage |
| Gate Tunneling | Thin oxide tunneling current |
| Non-Quasi-Static Effects (NQS) | High-frequency/RF simulation support |
| Self-Heating | Rth0 / Cth0 thermal network |
| Layout-Dependent Effects (LDE) | Parameterized stress model |

**BSIM-CMG Applicable Devices**:
- Double-Gate FinFET (DG-FinFET)
- Tri-Gate FinFET (TG-FinFET)
- Gate-All-Around Nanowire / Nanosheet (GAA-FET)
- Supports both SOI and Bulk substrates

---

### 3.6 BSIM-BULK (Originally BSIM6, ~2013)

**Positioning**: Next-generation model for bulk silicon planar MOSFETs. Core I-V uses **charge-based** method (based on inversion charge density), naturally satisfies Gummel symmetry at Vds=0.

**Comparison with BSIM4**:
- Parameter names fully compatible with BSIM4, facilitating migration
- Eliminates symmetry issues at Vds=0, suitable for harmonic and distortion analysis in analog/RF design
- Still limited to **planar bulk devices**, cannot be used for FinFETs

---

## IV. SPICE Level Number Reference

| SPICE Level | Model | Typical Simulators |
|-------------|------|-----------|
| 1 | Shichman-Hodges | All SPICE |
| 2 | Grove-Frohman | All SPICE |
| 3 | Semi-empirical short-channel | All SPICE |
| 8 / 49 | BSIM3v3 | HSPICE uses 49 |
| **54** | **BSIM4** | HSPICE standard |
| **72** | **BSIM-CMG** | HSPICE model cards |
| **107** | **BSIM-CMG** | **Xyce specific** |

> **Project Related**: BSIM-CMG uses `level=72` in HSPICE, but must use `level=107` in Xyce. The `get_compatible_model()` function in `src/utils.py` handles this level conversion while removing the `bulkmod` parameter unsupported by Xyce.

---

## V. Comparison of Three Core Modeling Methodologies

| Method | Representative Models | Core Variable | Advantages | Disadvantages |
|------|---------|---------|------|------|
| **Vth-based** | BSIM3, BSIM4 | Threshold voltage Vth | Fastest computation, most mature parameter extraction | Regional stitching causes derivative discontinuity (Gummel symmetry failure) |
| **Surface-Potential-based** | BSIM-CMG, BSIM-IMG, PSP | Surface potential ψs | Most physically rigorous, naturally adapts to thin-body/multi-gate devices | Requires iterative solution of implicit equations, higher computational cost |
| **Charge-based** | BSIM-BULK, EKV | Inversion charge density Qi | Naturally symmetric, continuous across regions, no iteration | Only applicable to bulk planar devices |

**Selection Logic**:
```
FinFET / GAA devices      → BSIM-CMG (surface potential, only choice)
Planar bulk + digital     → BSIM4 (most mature and stable, full PDK coverage)
Planar bulk + analog/RF   → BSIM-BULK (better symmetry)
```

---

## VI. Relation to SINOMOS Project

This project uses two types of BSIM models:

| Process Node | Device Type | Model | Level (Original→Xyce) |
|---------|---------|------|-------------------|
| 7nm, 10nm, 14nm, 16nm, 20nm | FinFET | BSIM-CMG | 72 → 107 |
| 22nm–180nm | Bulk CMOS | BSIM4 | 54 (unchanged) |

Model files from **PTM (Predictive Technology Model)**, a predictive model card set based on BSIM standards generated through physical extrapolation, used for academic research and early architecture exploration.

`src/utils.py:get_compatible_model()` does two things:
1. `level = 72` → `level = 107` (adapt Xyce's BSIM-CMG level number)
2. Remove `bulkmod = 1` (Xyce doesn't support this HSPICE attribute)

---

## VII. FinFET Device Structure

```
           Gate (tri-gate surrounding)
          ┌──────────┐
          │          │
  Source  │   Fin    │  Drain
  ────────┤  (vertical) ├────────
          │          │
          │          │
          └──────────┘
           STI / BOX
```

| Parameter | Meaning | Typical Value |
|------|------|--------|
| Hfin | Fin height | 30–50nm |
| Wfin | Fin width (must be < Lg/2 for electrostatic control) | <10nm |
| Lg | Gate length | 20nm → 5nm |
| Weff | Effective width = Nfin × (2×Hfin + Wfin) | — |
| Nfin | Number of fins (parallel to increase drive current) | 1–10+ |

**Evolution Direction**: FinFET (tri-gate, 22nm→5nm) → GAA / Nanosheet (gate-all-around, 3nm and below)

BSIM-CMG can uniformly support both FinFET and GAA devices by adjusting geometric parameters.

---

## VIII. References

- BSIM Official Website: https://bsim.berkeley.edu
- Chauhan et al., *FinFET Modeling for IC Simulation and Design Using the BSIM-CMG Standard*, Elsevier
- Liu & Hu, *BSIM4 and MOSFET Modeling for IC Simulation*, World Scientific
- *Celebrating 20 years of BSIM3v3 SPICE models*, Semiconductor Digest (2013)
- Compact Model Coalition: https://si2.org/cmc
- BSIM-CMG Technical Manual (official release from BSIM Group)